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| Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps AD8597/AD8599 FEATURES Low noise: 1.1 nV/Hz at 1 kHz Low distortion: -120 dB THD @ 1 kHz Input noise, 0.1 Hz to 10 Hz: <76 nV p-p Slew rate: 14 V/s Wide bandwidth: 10 MHz Supply current: 4.8 mA/amp typical Low offset voltage: 10 V typical CMRR: 120 dB Unity-gain stable 15 V operation PIN CONFIGURATIONS NC 1 -IN 2 +IN 3 8 NC V+ OUT 06274-060 06274-054 06274-061 AD8597 7 6 5 TOP VIEW V- 4 (Not to Scale) NC NC = NO CONNECT Figure 1. AD8597 8-Lead SOIC (R-8) NC 1 -IN 2 +IN 3 V- 4 PIN 1 INDICATOR 8 NC 7 V+ 6 OUT 5 NC AD8597 TOP VIEW APPLICATIONS Professional audio preamplifiers ATE/precision testers Imaging systems Medical/physiological measurements Precision detectors/instruments Precision data conversion NOTES 1. NC = NO CONNECT. 2. PIN 4 AND THE EXPOSED PAD MUST BE CONNECTED TO V-. Figure 2. AD8597 8-Lead LFCSP (CP-8-2) OUT A 1 -IN A 2 +IN A 3 8 +V OUT B -IN B +IN B AD8599 7 6 5 TOP VIEW -V 4 (Not to Scale) Figure 3. AD8599 8-Lead SOIC (R-8) GENERAL DESCRIPTION The AD8597/AD8599 are very low noise, low distortion operational amplifiers ideal for use as preamplifiers. The low noise of 1.1 nV/Hz and low harmonic distortion of -120 dB (or better) at audio bandwidths give the AD8597/AD8599 the wide dynamic range necessary for preamplifiers in audio, medical, and instrumentation applications. The excellent slew rate of 14 V/s and 10 MHz gain bandwidth make them highly suitable for medical applications. The low distortion and fast settling time make them ideal for buffering of high resolution data converters. The AD8597 is available in 8-lead SOIC and LFCSP packages, while the AD8599 is available in an 8-lead SOIC package. They are both specified over a -40C to +125C temperature range. The AD8597 and AD8599 are members of a growing series of low noise op amps offered by Analog Devices, Inc., (see Table 1). Table 1. Low Noise Op Amps Voltage Noise Single Dual Quad 0.9 nV AD797 1.1 nV AD8597 AD8599 1.8 nV 2.8 nV AD8675 AD8676 3.2 nV OP27 3.8 nV AD8671 AD8672 AD8674 ADA4004-4 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2008 Analog Devices, Inc. All rights reserved. AD8597/AD8599 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Power Sequencing ........................................................................ 5 ESD Caution...................................................................................5 Typical Performance Characteristics ..............................................6 Functional Operation..................................................................... 15 Input Voltage Range ................................................................... 15 Output Phase Reversal ............................................................... 15 Noise and Source Impedance Considerations ........................... 15 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 10/08--Rev.A to Rev. B Added AD8597 ................................................................... Universal Added LFCSP_VD ............................................................. Universal Added Table 1.................................................................................... 1 Changes to Specifications Section .................................................. 3 Changes to Absolute Maximum Ratings Section ......................... 5 Changes to Typical Performance Characteristics Section ........... 6 Added Figure 12 and Figure 15....................................................... 7 Added Figure 18 and Figure 19....................................................... 8 Added Figure 30 and Figure 33..................................................... 10 Added Figure 34 to Figure 38........................................................ 11 Added Figure 42 and Figure 45..................................................... 12 Added Figure 52, Figure 55, Figure 57......................................... 14 Added Functional Operation Section .......................................... 15 Added Figure 58.............................................................................. 15 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 4/07--Rev. 0 to Rev. A Updated Layout .................................................................................5 Changes to Figure 45 Caption ...................................................... 12 Added Figure 48 ............................................................................. 12 Changes to Figure 51 Caption ...................................................... 13 2/07--Revision 0: Initial Version Rev. B | Page 2 of 20 AD8597/AD8599 SPECIFICATIONS VSY = 5 V, VCM = 0 V, VO = 0 V, TA = 25C, unless otherwise specified. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol VOS -40C TA +125C Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance Differential Capacitance Common-Mode Capacitance OUTPUT CHARACTERISTICS Output Voltage High VOS/T IB IOS -40C TA +125C IVR CMRR AVO -2.0 V VCM +2.0 V -40C TA +125C RL 600 , VO = -11 V to +11 V -40C TA +125C -2.0 120 105 105 100 135 110 -40C TA +125C -40C TA +125C 65 0.8 40 Conditions Min Typ 15 Max 120 180 2.2 210 340 250 340 +2.0 Unit V V V/C nA nA nA nA V dB dB dB dB pF pF V V V V V V V V mA dB dB mA mA V/s V/s s MHz Degrees nV p-p nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz pA/Hz dB dB CDIFF CCM VOH RL = 600 -40C TA +125C RL = 2 k -40C TA +125C RL = 600 -40C TA +125C RL = 2 k -40C TA +125C At 1 MHz, AV = 1 VSY = 18 V to 4.5 V -40C TA +125C -40C TA +125C 120 118 3.5 3.3 3.7 3.5 15.4 5.5 3.7 3.8 -3.6 -3.7 52 5 140 4.8 5.5 6.5 -3.4 -3.3 -3.5 -3.4 Output Voltage Low VOL Output Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density Correlated Current Noise Uncorrelated Current Noise Total Harmonic Distortion + Noise Channel Separation ISC ZOUT PSRR ISY SR tS GBP M en p-p en AV = -1, RL = 2 k AV = 1, RL = 2 k To 0.01%, step = 10 V 14 14 2 10 60 76 1.07 2.0 4.2 2.4 5.2 -120 -120 THD + N CS 0.1 Hz to 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz G = 1, RL 1 k, f = 1 kHz, VRMS = 1 V f = 10 kHz Rev. B | Page 3 of 20 1.15 1.5 AD8597/AD8599 VS = 15 V, VCM = 0 V, VO = 0 V, TA = +25C, unless otherwise specified. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol VOS -40C TA +125C Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance Differential Capacitance Common-Mode Capacitance OUTPUT CHARACTERISTICS Output Voltage High VOS/T IB -40C TA +125C IOS -40C TA +125C IVR CMRR AVO -12.5 V VCM +12.5 V -40C TA +125C RL 600 , VO = -11 V to +11 V -40C TA +125C -12.5 120 115 110 106 135 116 50 -40C TA +125C 0.8 25 Conditions Min Typ 10 Max 120 180 2.2 200 300 200 300 +12.5 Unit V V V/C nA nA nA nA V dB dB dB dB pF pF V V V V V V V V mA dB dB mA mA V/s V/s s MHz Degrees nV p-p CDIFF CCM VOH RL = 600 -40C TA +125C RL = 2 k -40C TA +125C RL = 600 -40C TA +125C RL = 2 k -40C TA +125C At 1 MHz, AV = 1 VSY = 18 V to 4.5 V -40C TA +125C -40C TA +125C 120 118 13.1 12.8 13.5 13.2 12.1 5.1 13.4 13.7 -13.2 -13.5 52 5 140 5.0 5.7 6.75 -12.9 -12.8 -13.4 -13.3 Output Voltage Low VOL Output Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density Correlated Current Noise Uncorrelated Current Noise Total Harmonic Distortion + Noise Channel Separation ISC ZOUT PSRR ISY SR ts GBP M en p-p en AV = -1, RL = 2 k AV = 1, RL = 2 k To 0.01%, step = 10 V 16 15 2 10 65 76 1.07 1.9 4.3 2.3 5.3 -120 -120 THD + N CS 0.1 Hz to 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz f = 1 kHz f = 10 Hz G = 1, RL 1 k, f = 1 kHz, VRMS = 3 V f = 10 kHz Rev. B | Page 4 of 20 1.15 1.5 nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz pA/Hz dB dB AD8597/AD8599 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Input Voltage Differential Input Voltage1 Output Short-Circuit to GND Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 60 sec) Junction Temperature 1 THERMAL RESISTANCE Rating 18 V -V VIN +V 1 V Indefinite -65C to +150C -40C to +125C 300C 150C JA is specified with the device soldered on a circuit board with its exposed paddle soldered to a pad (if applicable) on a 4-layer JEDEC standard PCB with zero air flow. Table 5. Package Type 8-Lead LFCSP_VD (CP-8-2) 8-Lead SOIC (R-8) (AD8597) 8-Lead SOIC (R-8) (AD8599) JA 78 140 120 JC 20 39 36 Unit C/W C/W C/W If the differential input voltage exceeds 1 V, the current should be limited to 5 mA. POWER SEQUENCING The op amp supplies should be applied simultaneously. The op amp supplies should be stable before any input signals are applied. In any case, the input current must be limited to 5 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 20 AD8597/AD8599 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. 70 60 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 50 40 30 20 10 AD8599 MEAN = 8.23 STDEV = 24.47 MIN = -72.62 MAX = 62.09 VSY = 5V 70 60 50 40 30 20 10 AD8599 MEAN = 7.91 STDEV = 21.89 MIN = -63.02 MAX = 57.5 VSY = 15V Figure 4. Input Offset Voltage Distribution 60 45 40 35 30 25 20 15 10 5 06274-001 Figure 7. Input Offset Voltage Distribution 50 NUMBER OF AMPLIFIERS 40 30 20 10 NUMBER OF AMPLIFIERS AD8599 MEAN = 0.346 STDEV = 0.218 MIN = 0.010 MAX = 1.155 VSY = 5V AD8599 MEAN = 0.765 STDEV = 0.234 MIN = 0.338 MAX = 1.709 VSY = 15V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (V) 2.2 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (V) 2.2 2.4 Figure 5. TCVOS Distribution, -40C TA +125C Figure 8. TCVOS Distribution, -40C TA +125C 60 50 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 40 AD8599 MEAN = 0.461 STDEV = 0.245 MIN = 0.026 MAX = 1.26 VSY = 5V 60 50 40 AD8599 MEAN = 0.342 STDEV = 0.221 MIN = 0.013 MAX = 1.239 VSY = 15V 30 30 20 20 10 10 06274-006 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (V) 2.2 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TCVOS (V) 2.2 2.4 Figure 6. TCVOS Distribution, -40C TA +85C Figure 9. TCVOS Distribution, -40C TA +85C Rev. B | Page 6 of 20 06274-005 0 0 06274-007 06274-004 0 0 06274-002 0 -75 -65 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 VOS (V) 0 -75 -65 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 VOS (V) AD8597/AD8599 100 75 50 25 VOS (V) AD8599 VSY = 5V 100 75 50 25 VOS (V) AD8599 VSY = 15V 0 -25 -50 -75 06274-009 0 -25 -50 -75 06274-010 06274-063 06274-012 -100 -5.0 -2.5 0 VCM (V) 2.5 5.0 -100 -15 -10 -5 0 VCM (V) 5 10 15 Figure 10. Offset Voltage vs. VCM 350 300 250 200 150 AD8599 VSY = 5V VCM = 0V Figure 13. Offset Voltage vs. VCM 350 300 250 200 150 IB (nA) AD8599 VSY = 15V VCM = 0V IB (nA) 100 50 0 -50 100 50 0 -50 -100 -150 -25 0 25 50 TEMPERATURE (C) 75 100 125 06274-011 -100 -150 -200 -50 -25 0 25 50 TEMPERATURE (C) 75 100 125 -200 -50 Figure 11. Input Bias Current vs. Temperature 50 AD8597 40 30 20 VOS (V) Figure 14. Input Bias Current vs. Temperature 350 300 250 200 150 100 IB (nA) AD8597 VSY = 15V TA = -40C TA = +25C TA = +85C TA = +125C 10 0 -10 -20 5V -30 -40 -50 -50 -25 0 25 50 75 100 125 150 06274-062 50 0 -50 -100 -150 -200 -250 -300 -350 -12 -10 -8 -6 -4 -2 15V 0 VCM (V) 2 4 6 8 10 12 TEMPERATURE (C) Figure 12. Input Offset Voltage vs. Temperature Figure 15. Input Bias Current vs. Temperature Rev. B | Page 7 of 20 AD8597/AD8599 80 AD8599 70 60 50 50 IOS (nA) 100 150 AD8597 IB (nA) 40 IOS @ VSY = 5V 30 20 IOS @ VSY = 15V 10 06274-013 0 15V 5V -50 -100 06274-065 0 -50 -25 0 25 50 TEMPERATURE (C) 75 100 125 -150 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 16. Input Offset Current vs. Temperature 114 112 110 AD8599 VSY = 5V 118 RL = 2k, VO = 2V AVO (dB) Figure 19. Input Offset Current vs. Temperature 120 AD8599 VSY = 15V RL = 2k, VO = 11V AVO (dB) 108 106 104 RL = 600, VO = 2V 116 RL = 600, VO = 11V 114 112 102 100 -50 110 -50 06274-015 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 17. Large Signal Voltage Gain vs. Temperature 8 7 TA = +125C 6 5 TA = +85C TA = +25C 350 300 250 200 150 100 Figure 20. Large Signal Voltage Gain vs. Temperature AD8597 AD8599 VSY = 15V TA = -40C ISY (mA) 4 3 2 IB (nA) TA = -40C 50 0 -50 -100 -150 -200 -250 -300 -8 -6 -4 -350 -12 -10 TA = +25C TA = +85C TA = +125C 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VSY (V) -2 0 2 VCM (V) 4 6 8 10 12 Figure 18. Supply Current vs. Supply Voltage Figure 21. Input Bias Current vs. VCM Rev. B | Page 8 of 20 06274-014 0 06274-064 1 06274-016 AD8597/AD8599 80 60 40 20 0 -20 -40 -60 06274-017 AD8599 VSY = 5V ISINK 80 60 40 20 0 -20 -40 -60 ISINK AD8599 VSY = 15V OUTPUT CURRENT (mA) ISOURCE OUTPUT CURRENT (mA) ISOURCE -25 0 75 25 50 TEMPERATURE (C) 100 125 150 -25 0 75 25 50 TEMPERATURE (C) 100 125 150 Figure 22. ISC vs. Temperature 10k 10k OUTPUT SATURATION VOLTAGE (mV) Figure 25. ISC vs. Temperature OUTPUT SATURATION VOLTAGE (mV) AD8599 VSY = 5V AD8599 VSY = 15V ISINK 1k ISOURCE ISINK 1k ISOURCE 06274-021 0.01 0.1 IL (mA) 1 10 100 0.01 0.1 IL (mA) 1 10 100 Figure 23. Output Saturation Voltage vs. Current Load 2.5 AD8599 VSY = 5V 2.0 2.0 2.5 Figure 26. Output Saturation Voltage vs. Current Load AD8599 VSY = 15V VCC - VOH @ RL = 600 VCC - VOH (V) 1.5 VCC - VOH (V) VCC - VOH @ RL = 600 1.5 VCC - VOH @ RL = 2k 1.0 1.0 VCC - VOH @ RL = 2k 0.5 0.5 06274-027 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 -25 0 75 25 50 TEMPERATURE (C) 100 125 150 Figure 24. Output Saturation Voltage vs. Temperature Figure 27. Output Saturation Voltage vs. Temperature Rev. B | Page 9 of 20 06274-029 0 -50 0 -50 06274-022 100 0.001 100 0.001 06274-018 -80 -50 -80 -50 AD8597/AD8599 0 AD8599 VSY = 5V -0.5 0 AD8599 VSY = 15V -0.5 VEE - VOL (V) -1.0 VEE - VOL @ RL = 2k -1.5 VEE - VOL (V) -1.0 VEE - VOL @ RL = 2k -1.5 VEE - VOL @ RL = 600 -2.0 -2.0 VEE - VOL @ RL = 600 06274-028 -25 0 75 25 50 TEMPERATURE (C) 100 125 150 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 28. Output Saturation Voltage vs. Temperature Figure 31. Output Saturation Voltage vs. Temperature -13.0 VOL @ RL = 600 15.0 14.8 14.6 AD8599 VSY = 15V -13.5 VOL @ RL = 2k VOH (V) 14.4 14.2 VOL (V) -14.0 14.0 13.8 13.6 VOH @ RL = 2k -14.5 13.4 AD8599 VSY = 15V 0 50 TEMPERATURE (C) 100 150 06274-032 VOH @ RL = 600 13.2 0 50 TEMPERATURE (C) 100 150 06274-031 06274-067 -15.0 -50 13.0 -50 Figure 29. Output Voltage Low vs. Temperature 100 80 Figure 32. Output Voltage High vs. Temperature 120 100 GAIN (dB) AND PHASE (Degrees) GAIN (dB) AND PHASE (Degrees) 60 40 20 0 -20 -40 -60 -80 -100 10 AD8597 VSY = 5V RL = 2k 100 1k FREQUENCY (kHz) 10k 50k CL = 200pF CL = 20pF 80 60 40 20 0 -20 -40 -60 -80 1 10 100 1k 10k 50k FREQUENCY (kHz) CL = 200pF AD8597 VSY = 15V RL = 2k CL = 20pF Figure 30. Gain and Phase vs. Frequency 06274-066 Figure 33. Gain and Phase vs. Frequency Rev. B | Page 10 of 20 06274-030 -2.5 -50 -2.5 -50 AD8597/AD8599 50 40 30 20 GAIN (dB) 50 AV = 100 40 30 AV = 10 20 GAIN (dB) AV = 100 AV = 10 10 0 -10 -20 06274-068 10 0 -10 -20 06274-071 AV = 1 AV = 1 -30 -40 1 AD8597 VSY = 5V RL = 2k 10 100 1k 10k 50k -30 -40 1 AD8597 VSY = 15V RL = 2k 10 100 1k 10k 50k FREQUENCY (kHz) FREQUENCY (kHz) Figure 34. Closed-Loop Gain vs. Frequency 100 AV = -100 10 AV = -10 ZOUT () ZOUT () Figure 37. Closed-Loop Gain vs. Frequency 100 AV = -100 10 AV = -10 AV = +1 1 AV = +1 1 0.1 06274-069 0.1 AD8597 VSY = 5V AD8597 VSY = 15V 0.01 10 100 1k FREQUENCY (kHz) 10k 06274-072 0.01 10 100 1k FREQUENCY (kHz) 10k 100k 100k Figure 35. Closed-Loop Output Impedance vs. Frequency 110 100 100 90 80 CMRR (dB) Figure 38. Closed-Loop Output Impedance vs. Frequency 120 AD8599 5V VSY 15V PSRR+ (dB) PSRR- (dB) 80 PSRR (dB) 06274-070 70 60 50 40 30 20 1 10 100 FREQUENCY (kHz) 1k 10k AD8597 VSY = 5V, 15V 60 40 20 0 -20 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 36. Common-Mode Rejection Ratio vs. Frequency Figure 39. Power Supply Rejection Ratio vs. Frequency Rev. B | Page 11 of 20 06274-038 AD8597/AD8599 90 80 70 60 50 40 30 20 10 06274-039 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS AD8599 MEAN = 1.30 STDEV = 0.09 MIN = 1.1 MAX = 1.5 5V VSY 15V 600 500 400 AD8599 MEAN = 1.07 STDEV = 0.02 MIN = 1.05 MAX = 1.15 5V VSY 15V 300 200 100 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 VOLTAGE NOISE DENSITY (nV/ Hz) 2.0 0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19 VOLTAGE NOISE DENSITY (nV/ Hz) Figure 40. Voltage Noise Density @ 10 Hz 100 AD8599 5V VSY 15V VOLTAGE NOISE DENSITY (nV/ Hz) Figure 43. Voltage Noise Density @ 1 kHz 100 AD8599 5V VSY 15V CURRTENT NOISE DENSITY (pA/ Hz) 10 10 1 1 06274-041 1 10 100 FREQUENCY (Hz) 1k 1 10 100 FREQUENCY (Hz) 1k Figure 41. Voltage Noise Density vs. Frequency Figure 44. Current Noise Density vs. Frequency 1 1 0.1 RL = 600 0.01 AD8597 VSY = 5V AV = +1 0.001 06274-073 0.1 THD + N (%) THD + N (%) 0.01 AD8597 VSY = 15V AV = +1 0.001 RL = 600 0.0001 0.001 RL = 100k 0.01 0.1 V rms (V) 1 10 0.0001 0.001 RL = 100k 0.01 0.1 V rms (V) 1 10 Figure 42. THD + N vs. Amplitude Figure 45. THD + N vs. Amplitude Rev. B | Page 12 of 20 06274-074 06274-042 0.1 0.1 06274-040 0 0 AD8597/AD8599 0.1 AD8599 VSY = 15V VIN = 3V rms VIN = 5V rms VIN = 7V rms 0.01 THD + N (%) 0.1 AD8599 VSY = 15V VIN = 3V rms 0.01 THD + N (%) 0.001 0.001 RL = 600 RL = 2k 0.0001 10 0.0001 10 06274-044 100 1k FREQUENCY (Hz) 10k 100k 100 1k FREQUENCY (Hz) 10k 100k Figure 46. THD + N vs. Frequency Figure 49. THD + N vs. Frequency 20 AD8599 15 10 AMPLITUDE (V) AMPLITUDE (V) 20 AD8599 15 10 5 0 -5 -10 -15 06274-047 5 0 -5 -10 -15 -20 -8.6 VSY = 15V VIN = 20V p-p AV = 1 RF = 1k RL = 2k VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4s/DIV VSY = 15V VIN = 20V p-p AV = -1 RF = 2k RS = 2k CL = 0pF VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4s/DIV 06274-048 -4.6 -0.6 3.4 7.4 11.4 15.4 TIME (s) 19.4 23.4 27.4 31.4 -20 -8.6 -4.6 -0.6 3.4 7.4 11.4 15.4 TIME (s) 19.4 23.4 27.4 31.4 Figure 47. Large Signal Response Figure 50. Large Signal Response 80 AD8599 60 40 AMPLITUDE (mV) 45 40 35 AD8599 5V VSY 15V AV = 1 RL = 10k 20 0 -20 -40 -60 -80 -800 -400 VSY = 15V, 5V VIN = 100mV p-p AV = 1 EXTERNAL CL = 100pF EXTERNAL RL = 10k VERTICAL AXIS = 20mV/DIV HORIZONTAL AXIS = 400ns/DIV 06274-046 OVERSHOOT (%) 30 25 20 15 10 5 100 CAPACITANCE (pF) 1k 06274-049 0 400 800 1200 1600 2000 2400 2800 3200 TIME (ns) 0 10 Figure 48. Small Signal Response Figure 51. Overshoot vs. Capacitance Rev. B | Page 13 of 20 06274-043 AD8597/AD8599 45 40 35 AD8597 VSY = 5V 45 40 35 OS- AD8597 VSY = 15V OVERSHOOT (%) 25 20 OS- 15 OS+ 10 06247-077 OVERSHOOT (%) 30 30 25 20 15 10 5 0 10 OS+ 06247-078 5 0 10 100 CAPACITANCE (pF) 1k 100 CAPACITANCE (pF) 1k Figure 52. Overshoot vs. Capacitive Load 0 -20 CHANNEL SEPARATION (dB) -40 -60 -80 -100 -120 -140 06274-050 Figure 55. Overshoot vs. Capacitive Load 15.0 AD8599 AD8599 VSY = 15V AV = 100 RL = 1k VIN = 10V p-p VIN = 20V p-p 12.5 ISY (mA) 10.0 VSY = 15V VSY = 5V 7.5 1k 10k FREQUENCY (Hz) 100k 1M -25 0 25 50 TEMPERATURE (C) 75 100 125 Figure 53. Channel Separation vs. Frequency Figure 56. Supply Current vs. Temperature 800 600 400 AD8599 5V VSY 15V 6.0 AD8597 5.5 VSY = 15V AMPLITUDE (nV) 200 ISY (mA) 0 -200 -400 -600 06274-053 5.0 VSY = 5V 4.5 06274-075 -800 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 54. Peak-to-Peak Noise Figure 57. Supply Current vs. Temperature Rev. B | Page 14 of 20 06274-020 -160 100 5.0 -50 AD8597/AD8599 FUNCTIONAL OPERATION INPUT VOLTAGE RANGE The AD8597/AD8599 are not rail-to-rail input amplifiers; therefore, care is required to ensure that both inputs do not exceed the input voltage range. Under normal negative feedback operating conditions, the amplifier corrects its output to ensure that the two inputs are at the same voltage. However, if either input exceeds the input voltage range, the loop opens and large currents begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and they are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes can become forward-biased. Without current limiting, excessive amounts of current may flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, insert appropriate series resistors to limit the diode current to less than 5 mA maximum. The input stage has two diodes between the input pins to protect the differential pair. Under high slew rate conditions, when the op amp is connected as a voltage follower, the diodes may become forward-biased and the source may try to drive the output. A small resistor should be placed in the feedback loop and in the noninverting input. The noise of a 100 resistor at room temperature is ~1.25 nV/Hz, which is higher than the AD8597/AD8599. Thus, there is a tradeoff between noise performance and protection. If possible, limiting should be placed earlier in the signal path. For further details, see the Amplifier Input Protection...Friend or Foe article at http://www.analog.com/amplifier_input. Because of the large transistors used to achieve low noise, the input capacitance may seem rather high. To take advantage of the low noise performance, impedance around the op amp should be low, less than 500 . Under these conditions, the pole from the input capacitance should be greater than 50 MHz, which does not affect the signal bandwidth. The AD8597/AD8599 amplifiers have been carefully designed to prevent any output phase reversal if both inputs are maintained within the specified input voltage range. If one or both inputs exceed the input voltage range but remain within the supply rails, the op amp specifications, such as CMRR, are not guaranteed, but the output remains close to the correct value. NOISE AND SOURCE IMPEDANCE CONSIDERATIONS The AD8597/AD8599 ultralow voltage noise of 1.1 nV/Hz is achieved with special input transistors running at high collector current. Therefore, it is important to consider the total inputreferred noise (eN total), which includes contributions from voltage noise (eN), current noise (iN), and resistor noise (4 kTRS). eN total = [eN2 + 4 kTRS + (iN x RS)2]1/2 where RS is the total input source resistance. This equation is plotted for the AD8597/AD8599 in Figure 58. Because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total RS by a factor of 2. At a very low source resistance (RS < 50 ), the voltage noise of the amplifier dominates. As source resistance increases, the Johnson noise of RS dominates until a higher resistance of RS > 2 k is achieved; the current noise component is larger than the resistor noise. 100 (1) TOTAL NOISE (nV/ Hz) 10 TOTAL NOISE RESISTOR NOISE ONLY 1 OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As the commonmode voltage is moved outside the input voltage range, the outputs of these amplifiers can suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down that causes a radical shifting of internal voltages that results in the erratic output behavior. 0.1 10 100 1k 10k SOURCE RESISTANCE () Figure 58. Noise vs. Source Resistance Rev. B | Page 15 of 20 06274-076 AD8597/AD8599 The AD8597/AD8599 are the optimum choice for low noise performance if the source resistance is kept < 1 k. At higher values of source resistance, optimum performance with respect to only noise is obtained with other amplifiers from Analog Devices. Both voltage noise and current noise need to be considered. For more information on avoiding noise from grounding problems and inadequate bypassing, see the AN-345 Application Note, Grounding for Low- and High-Frequency Circuits. For V+ general noise theory with extensive calculations, see the AN-358 Application Note, Noise and Operational Amplifier Circuits. A good selection table for low noise op amps can be found in AN-940 Application Note, Low Noise Amplifier Selection Guide for Optimal Noise Performance. An interesting note on using one section of a monolithic dual to phase compensate the other section is in the AN-107 Application Note, Active Feedback Improves Amplifier Phase Accuracy. 7 Q36 R18 D1 D31 2 D34 Q18 Q19 D39 D41 D42 Q32 D2 Q27 4 Q28 06247-079 R19 R31 D2 6 OUTPUT INVERTING - INPUT VB Q19 Q20 C1 R1 D3 R32 3 NONINVERTING + INPUT D40 V- Figure 59. Simplified Schematic Rev. B | Page 16 of 20 AD8597/AD8599 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.25 3.00 SQ 2.75 0.60 MAX 0.60 MAX 5 8 0.50 BSC PIN 1 INDICATOR TOP VIEW 2.95 2.75 SQ 2.55 EXPOSED PAD (BOT TOM VIEW) 1.60 1.45 1.30 PIN 1 INDICATOR 4 1 0.90 MAX 0.85 NOM SEATING PLANE 12 MAX 0.70 MAX 0.65 TYP 0.50 0.40 0.30 0.05 MAX 0.01 NOM 1.89 1.74 1.59 Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8597ACPZ-R2 1 AD8597ACPZ-REEL1 AD8597ACPZ-REEL71 AD8597ARZ1 AD8597ARZ-REEL1 AD8597ARZ-REEL71 AD8599ARZ1 AD8599ARZ-REEL1 AD8599ARZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Package Option CP-8-2 CP-8-2 CP-8-2 R-8 R-8 R-8 R-8 R-8 R-8 101708-B 0.30 0.23 0.18 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS SECTION OF THIS DATA SHEET. 012407-A Branding A22 A22 A22 Z = RoHS Complaint Part. Rev. B | Page 17 of 20 AD8597/AD8599 NOTES Rev. B | Page 18 of 20 AD8597/AD8599 NOTES Rev. B | Page 19 of 20 AD8597/AD8599 NOTES (c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06274-0-10/08(B) Rev. B | Page 20 of 20 |
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